A Flexible High-Bandwidth Low-Latency Multi-Port Memory Controller

摘要

Multi-port memory controllers (MPMCs) have become increasingly important inmany modern applications due to the tremendous growth in bandwidth requirement.Many approaches so far have focused on improving either the memory accesslatency or the bandwidth utilization for specific applications. Moreover, theapplication systems are likely to require certain adjustments to connect withan MPMC, since the MPMC interface is limited to a single-clock and singledata-width domain. In this paper, we propose efficient techniques to improvethe flexibility, latency, and bandwidth of an MPMC. Firstly, MPMC interfacesemploy a pair of dual-clock dual-port FIFOs at each port, so any multi-clockmulti-data-width application system can connect to an MPMC without requiringextra resources. Secondly, memory access latency is significantly reducedbecause parallel FIFOs temporarily keep the data transfer between theapplication system and memory. Lastly, a proposed arbitration scheme, namelywindow-based first-come-first-serve, considerably enhances the bandwidthutilization. Depending on the applications, MPMC can be properly configured byupdating several internal configuration registers. The experimental results inan Altera Cyclone FPGA prove that MPMC is fully operational at 150 MHz andsupports up to 32 concurrent connections at various clocks and data widths.More significantly, achieved bandwidth utilization is approximately 93.2% ofthe theoretical bandwidth, and the access latency is minimized as compared toprevious designs.